Video Processing in an FPGA-Enabled Ethernet Switch

Metadata

Publisher: SMPTE — White Plains, NY
Doc Type: Conference Paper
Content Type: Original Research
Volume: 2013, No. 10, pp. 1–10
Abstract: Carriage of uncompressed HD video using IP holds great potential for enhancing the flexibility of broadcast plants while reducing the number of cables required through aggregation of signals using statistical multiplexing. The broadcast industry is just beginning to determine the appropriate architectures to best utilize professional video-over-IP capabilities. The Arista 7124FX Application Switch is a 10GbE data center class Ethernet switch that also supports application acceleration through the use of an on-board FPGA (Field Programmable Gate Array) without adding network jitter. A proof-of-concept has been developed to show how an FPGA-enabled switch can perform frame accurate video stream switching of SMPTE 2022-6 RTP flows.
Publication Date: 2013-10-01
DOI: 10.5594/M001498
Link: https://doi.org/10.5594/M001498
Author(s): Thomas EdwardsFOX, 10201 W. Pico Blvd, Los Angeles CA, 90035
Warren BelkinArista Networks, 5453 Great America Parkway, Santa Clara, CA 95054
Andy BechtolsheimArista Networks, 5453 Great America Parkway, Santa Clara, CA 95054
Keyword(s): FPGA, Ethernet, SDI, RTP
Copyright: © 2013 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

1. Laabs M. , “SDI Over IP — Seamless Signal Switching in SMPTE 2022-6 and a Novel Multicast Routing Concept,” EBU Technical Review , 2012 Q4. EXTERNAL
2. SMPTE ST 2022-6:2012, “Transport of High Bit Rate Media Signals over IP Networks (HBRMT)” . EXTERNAL
3. Kouadio A. , “SDI over IP interoperability tests,” presented at the EBU Network Technology Seminar 2013, Geneva, CH, June 2013 . EXTERNAL
4. Pro-MPEG Code of Practice #4 release 1, “Transmission of High Bit Rate Studio Streams over IP Networks” . EXTERNAL
5. SMPTE ST 296:2012, “1280 × 720 Progressive Image 4:2:2 and 4:4:4 Sample Structure — Analog and Digital Representation and Analog Interface” . EXTERNAL
6. SMPTE ST 292-1:2013, “1.5 Gb/s Signal/Data Serial Interface” . EXTERNAL
7. SMPTE RP 168:2009, “Definition of Vertical Interval Switching Point for Synchronous Video Switching” . EXTERNAL
8. IEEE Standard 1588-2008, “IEEE Standard for a Precision Clock Synchronization Protocol or Networked Measurement and Control Systems” . EXTERNAL

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Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; Video Processing in an FPGA-Enabled Ethernet Switch, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013. Available at https://doi.org/10.5594/M001498

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Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; Video Processing in an FPGA-Enabled Ethernet Switch, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013. Available at https://doi.org/10.5594/M001498

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<span class="citation">Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; <cite>Video Processing in an FPGA-Enabled Ethernet Switch</cite>, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013. Available at <a href="https://doi.org/10.5594/M001498" target="_blank" rel="noopener">https://doi.org/10.5594/M001498</a></span>

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Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; Video Processing in an FPGA-Enabled Ethernet Switch, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013
doi: 10.5594/M001498
url: https://doi.org/10.5594/M001498

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Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; <cite id="bib-10-5594-m001498">Video Processing in an FPGA-Enabled Ethernet Switch</cite>, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013
<span class="doi">10.5594/M001498</span>
</li>