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Current document root: SMPTE Motion Imaging Journal ( Volume: 123, Issue: 4, May 2014)

A Design Approach to Creating Scalable Video Processing Systems beyond UHDTV1 on an FPGA

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1. AN464 , “4K Format Conversion Reference Design,” http://www.altera.com/literature/an/an646.pdfEXTERNAL
10. “Japan Starts 4K Ultra HD Broadcasting July 2014,” NextPowerUP , Jan. 2013 , http://www.nextpowerup.com/news/645/japan-starts-4k-ultrahd-broadcasting-july-2014.html .EXTERNAL
11. AN679 “High-Definition Video Reference Design (UDX 6),” http://www.altera.com/literature/an/an_679_udx6.pdfEXTERNAL
12. “Video and Image Processing Suite User Guide,” http://www.altera.com/literature/ug/ug_vip.pdfEXTERNAL
13. Cope B. “Video Processing Acceleration using Reconfigurable Logic and Graphics Processors,” Ph.D. dissertation, Dept. of Electronic and Electrical Engineering, Imperial College London , 2008 .EXTERNAL
2. AN648 , “Multioutput Scaler Reference Design,” http://www.altera.com/literature/an/an648.pdfEXTERNAL
3. AN654 , “Video and Image Processing Component Library,” http://www.altera.com/literature/an/an654.pdfEXTERNAL
4. DisplayPort1.2, VESA DisplayPort Standard version 1, revision 2a, May 23, 2012. http://www.vesa.org/vesa-standards/standards-summaries/EXTERNAL
5. HDMI2.0 Press Release, http://www.hdmi.org/press/press_release.aspx?prid=133EXTERNAL
6. SMPTE 424M ( 2012 ), “3 Gb/s Signal/Data Serial Interface,” http://standards.smpte.org .EXTERNAL
7. SMPTE 425M : 2011 , “Source Image Format and Ancillary Data Mapping for the 3 Gb/s Serial Interface,” http://standards.smpte.orgEXTERNAL
8. TV Logic LUM 560W product information, http://www.tvlogicusa.com/product/product.php?model=LUM-560WEXTERNAL
9. SMPTE ST 2022-6 ( 2012 ), “Transport of High Bit Rate Media Signals Over IP Networks (HBRMT),” http://standards.smpte.org .EXTERNAL