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SMPTE ST 425-5:2019
[ACTIVE]

Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface

Metadata

Publisher
SMPTE
Doc Type
Standard (ST)
Release Tag
20190304-pub
Publication Date
2019-03-04
DOI
10.5594/SMPTE.ST425-5.2019
Link
https://doi.org/10.5594/SMPTE.ST425-5.2019
Latest version of SMPTE ST 425-5

Document Suite — SMPTE ST 425-5

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Plain text (ISO 690 compliant)

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SMPTE ST 425-5:2019, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface. Available at https://doi.org/10.5594/SMPTE.ST425-5.2019
Snippet:
SMPTE ST 425-5:2019, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface. Available at https://doi.org/10.5594/SMPTE.ST425-5.2019
Undated variant
Preview:
SMPTE ST 425-5, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface. Available at https://doi.org/10.5594/SMPTE.ST425-5
Snippet:
SMPTE ST 425-5, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface. Available at https://doi.org/10.5594/SMPTE.ST425-5

HTML (ISO 690 compliant)

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SMPTE ST 425-5:2019, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface. Available at https://doi.org/10.5594/SMPTE.ST425-5.2019
Snippet:
<span class="citation"><cite>SMPTE ST 425-5:2019</cite>, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface. Available at <a href="https://doi.org/10.5594/SMPTE.ST425-5.2019" target="_blank" rel="noopener">https://doi.org/10.5594/SMPTE.ST425-5.2019</a></span>
Undated variant
Preview:
SMPTE ST 425-5, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface. Available at https://doi.org/10.5594/SMPTE.ST425-5
Snippet:
<span class="citation"><cite>SMPTE ST 425-5</cite>, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface. Available at <a href="https://doi.org/10.5594/SMPTE.ST425-5" target="_blank" rel="noopener">https://doi.org/10.5594/SMPTE.ST425-5</a></span>

SMPTE Icon SMPTE's HTML Pub

Preview:
SMPTE ST 425-5:2019, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface
doi: 10.5594/SMPTE.ST425-5.2019
url: https://doi.org/10.5594/SMPTE.ST425-5.2019
Snippet:
<li>
<cite id="bib-smpte-st425-5-2019">SMPTE ST 425-5:2019</cite>, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface
<span class="doi">10.5594/SMPTE.ST425-5.2019</span>
</li>
Undated variant
Preview:
SMPTE ST 425-5, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface
doi: 10.5594/SMPTE.ST425-5
url: https://doi.org/10.5594/SMPTE.ST425-5
Snippet:
<li>
<cite id="bib-smpte-st425-5-2019">SMPTE ST 425-5</cite>, Bit-Serial Interfaces at 3 Gb/s — Image Format and Ancillary Data Mapping for the Quad Link 3 Gb/s Serial Interface
<span class="doi">10.5594/SMPTE.ST425-5</span>
</li>