Video Processing in an FPGA-Enabled Ethernet Switch

Metadata

Publisher: SMPTE — White Plains, NY, USA
Doc Type: Journal Article
Content Type: Original Research
Abbreviated Title: SMPTE Mot. Imag. J
Volume: 123, No. 2, pp. 48–52
Abstract: Carriage of uncompressed high-definition video using Internet protocol (IP) holds great potential for enhancing the flexibility of broadcast plants while reducing the number of cables required through aggregation of signals using statistical multiplexing. The broadcast industry is just beginning to determine the appropriate architectures to best use professional video-over-IP capabilities. The Arista 7124FX application switch is a 10 Gbit Ethernet data center-class Ethernet switch that also supports application acceleration through the use of an onboard field programmable gate array (FPGA) without adding network jitter. A proof of concept has been developed to show how an FPGA-enabled switch can perform frame-accurate video stream switching of SMPTE ST 2022-6:2012 realtime protocol flows.
Publication Date: 2014-03-01
DOI: 10.5594/j18384
ISSN: Print: 1545-0279
Link: https://doi.org/10.5594/j18384
Author(s): Thomas Edwards
Warren Belkin
Andy Bechtolsheim
Copyright: © 2014 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

1. Laabs M. , “SDI Over IP—Seamless Signal Switching in SMPTE 2022-6 and a Novel Multicast Routing Concept,” EBU Technical Review , Q4 , 2012 . EXTERNAL
2. SMPTE ST 2022-6 , “Transport of High Bit Rate Media Signals over IP Networks (HBRMT),” 2012 . http://standards.smpte.org . EXTERNAL
3. Kouadio A. , “SDI over IP Interoperability Tests,” presented at the EBU Network Technology Seminar, Geneva, Switzerland , June 2013 . EXTERNAL
4. Pro-MPEG Code of Practice No. 4, Release 1 , “Transmission of High Bit Rate Studio Streams over IP Networks,” July 2004 . EXTERNAL
5. SMPTE ST 296 , “1280 × 720 Progressive Image 4:2:2 and 4:4:4 Sample Structure—Analog and Digital Representation and Analog Interface,” 2012 . EXTERNAL
6. SMPTE ST 292-1 , “1.5 Gb/s Signal/Data Serial Interface,” 2013 . EXTERNAL
7. GitHub , “FoxNeo Advanced Technology: SMPTE 2022-6 Dissector,” https://github.com/FOXNEOAdvancedTechnology/smpte2022-6-dissector . EXTERNAL
8. SMPTE RP 168 , “Definition of Vertical Interval Switching Point for Synchronous Video Switching,” 2009 . EXTERNAL
9. IEEE Standard 1588 , “IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems,” 2008 . EXTERNAL

Source Data (JSON)

Full registry record with provenance metadata. Open directly: /api/doc/10.5594-j18384.json

Reference Tree

Explore all references and references to this document, as a navigable tree.

Open Reference Tree

Reference this Doc

Plain text (ISO 690 compliant)

Preview:

Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; Video Processing in an FPGA-Enabled Ethernet Switch, SMPTE Motion Imaging Journal ( Volume: 123, Issue: 2, March 2014); SMPTE, 2014. Available at https://doi.org/10.5594/j18384

Snippet:

Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; Video Processing in an FPGA-Enabled Ethernet Switch, SMPTE Motion Imaging Journal ( Volume: 123, Issue: 2, March 2014); SMPTE, 2014. Available at https://doi.org/10.5594/j18384

HTML (ISO 690 compliant)

Preview:

Snippet:

<span class="citation">Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; <cite>Video Processing in an FPGA-Enabled Ethernet Switch</cite>, SMPTE Motion Imaging Journal ( Volume: 123, Issue: 2, March 2014); SMPTE, 2014. Available at <a href="https://doi.org/10.5594/j18384" target="_blank" rel="noopener">https://doi.org/10.5594/j18384</a></span>

SMPTE's HTML Pub

Preview:

Snippet:

<li>
Thomas Edwards, Warren Belkin, and Andy Bechtolsheim; <cite id="bib-10-5594-j18384">Video Processing in an FPGA-Enabled Ethernet Switch</cite>, SMPTE Motion Imaging Journal ( Volume: 123, Issue: 2, March 2014); SMPTE, 2014
<span class="doi">10.5594/j18384</span>
</li>

Referenced By

A Practical Approach to IP Live Production [Active]