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SMPTE Meetings and Conferences ( November 2021)
[ACTIVE]

Tighter NIC/GPU Integration Yields Next Level Media Processing Performance

Metadata

Publisher
SMPTE — White Plains, NY, USA
Doc Type
Conference Paper
Content Type
Original Research
Volume
2021, No. 11, pp. 1–17
Abstract
As the media industry further consolidates building services based on Commercial-Off-The-Shelf (COTS) hardware, the requirement for increasing performance continues to accelerate. The processing of video resolutions up to Ultra HD (UHD) and 8K, higher frame rates, increased bit depth, and High Dynamic Range (HDR) imagery, requires tighter integration and optimization between the Network Interface Controller (NIC) and the Graphical Processing Unit (GPU). Combined with simultaneous input and output of multiple streams, this creates the potential for performance bottlenecks that must be unlocked. — This paper describes how COTS hardware platforms running GPUs alongside ST 2059-2 PTP locked NICs which are accurately pacing packets according to ST 2110-21 requirements may further increase their performance throughput by reducing CPU driven data copy overhead. And in doing so, reduce processing latency and jitter, and more effectively use GPU resources while freeing up CPU resources.
Publication Date
2021-11-09
DOI
10.5594/M001948
Link
https://doi.org/10.5594/M001948
Author(s)
Thomas KernenNVIDIA
Thomas TrueNVIDIA
Keyword(s)
GPU, NIC, Data Processing Unit (DPU), PTP, ST 2110, Timing
Copyright
© 2021 Society of Motion Picture and Television Engineers, Inc.

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Thomas Kernen and Thomas True; Tighter NIC/GPU Integration Yields Next Level Media Processing Performance, SMPTE Meetings and Conferences ( November 2021); SMPTE, 2021. Available at https://doi.org/10.5594/M001948
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Thomas Kernen and Thomas True; Tighter NIC/GPU Integration Yields Next Level Media Processing Performance, SMPTE Meetings and Conferences ( November 2021); SMPTE, 2021. Available at https://doi.org/10.5594/M001948

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Thomas Kernen and Thomas True; Tighter NIC/GPU Integration Yields Next Level Media Processing Performance, SMPTE Meetings and Conferences ( November 2021); SMPTE, 2021. Available at https://doi.org/10.5594/M001948
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<span class="citation">Thomas Kernen and Thomas True; <cite>Tighter NIC/GPU Integration Yields Next Level Media Processing Performance</cite>, SMPTE Meetings and Conferences ( November 2021); SMPTE, 2021. Available at <a href="https://doi.org/10.5594/M001948" target="_blank" rel="noopener">https://doi.org/10.5594/M001948</a></span>

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Thomas Kernen and Thomas True; Tighter NIC/GPU Integration Yields Next Level Media Processing Performance, SMPTE Meetings and Conferences ( November 2021); SMPTE, 2021
doi: 10.5594/M001948
url: https://doi.org/10.5594/M001948
Snippet:
<li>
Thomas Kernen and Thomas True; <cite id="bib-10-5594-m001948">Tighter NIC/GPU Integration Yields Next Level Media Processing Performance</cite>, SMPTE Meetings and Conferences ( November 2021); SMPTE, 2021
<span class="doi">10.5594/M001948</span>
</li>