A Design Approach to Creating Scalable Beyond-4K Video Processing Systems on FPGAs

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Publisher: SMPTE — White Plains, NY
Doc Type: Conference Paper
Content Type: Original Research
Volume: 2013, No. 10, pp. 1–20
Abstract: An unquenchable end-user thirst for enhanced video quality results in an ever-scaling video frame size and frame rate requirements. As we move from 4K to 8K and 120fps to 300fps, inevitably the computational complexity of video processing systems required to consume, process and deliver video content increases. The need for solutions to support combinations of frame sizes and rates, as well as future increments, emphasizes the need for system scalability. The computational complexity and scalability requirements pose exciting challenges for FPGA implementation of video processing pipelines. This paper presents implementation techniques and methodologies to overcome these challenges. We specifically concentrate on architectures whereby the input per-pixel video sample rate exceeds the system clock rate. Novel results include classifying pixel processing orders and presenting a component-based design approach for future-proofing video processing solutions against an ever-scaling computational complexity requirement. Resource and memory bandwidth requirements of such systems are also analysed and trends presented.
Publication Date: 2013-10-01
DOI: 10.5594/M001527
Link: https://doi.org/10.5594/M001527
Author(s): Benjamin CopeAltera Europe, High Wycombe, Buckinghamshire, UK
David ShihAltera Corporation, San Jose, California, USA
Keyword(s): FPGA, 4K
Copyright: © 2013 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

1. Cope B. , “Video Processing Acceleration using Reconfigurable Logic and Graphics Processors,” Ph.D. dissertation, Dept. of Electronic and Electrical Engineering, Imperial College London , 2008 . EXTERNAL
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11. SMPTE 424M, “3 Gb/s Signal/Data Serial Interface,” SMPTE Mot. Imag. J. , 424 , Oct. 2012 . EXTERNAL
12. SMPTE 425M, “Source Image Format and Ancillary Data Mapping for the 3 Gb/s Serial Interface,” SMPTE Mot. Imag. J. , 425 – 1 , Mar. 2011 . EXTERNAL
2. AN679 “High-Definition Video Reference Design (UDX 6)” http://www.altera.com/literature/an/an_679_udx6.pdf . EXTERNAL
3. AN464 “4K Format Conversion Reference Design” http://www.altera.com/literature/an/an646.pdf . EXTERNAL
4. AN648 “Multioutput Scaler Reference Design” http://www.altera.com/literature/an/an648.pdf . EXTERNAL
5. AN654 “Video and Image Processing Component Library” http://www.altera.com/literature/an/an654.pdf . EXTERNAL
6. “Video and Image Processing Suite User Guide” http://www.altera.com/literature/ug/ug_vip.pdf . EXTERNAL
7. DisplayPort1.2 VESA DisplayPort Standard version 1, revision 2a, May 23, 2012. EXTERNAL
8. HDMI2.0 Press Release http://www.hdmi.org/press/press_release.aspx?prid=133 . EXTERNAL
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Benjamin Cope and David Shih; A Design Approach to Creating Scalable Beyond-4K Video Processing Systems on FPGAs, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013. Available at https://doi.org/10.5594/M001527

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Benjamin Cope and David Shih; A Design Approach to Creating Scalable Beyond-4K Video Processing Systems on FPGAs, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013. Available at https://doi.org/10.5594/M001527

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<span class="citation">Benjamin Cope and David Shih; <cite>A Design Approach to Creating Scalable Beyond-4K Video Processing Systems on FPGAs</cite>, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013. Available at <a href="https://doi.org/10.5594/M001527" target="_blank" rel="noopener">https://doi.org/10.5594/M001527</a></span>

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Benjamin Cope and David Shih; A Design Approach to Creating Scalable Beyond-4K Video Processing Systems on FPGAs, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013
doi: 10.5594/M001527
url: https://doi.org/10.5594/M001527

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Benjamin Cope and David Shih; <cite id="bib-10-5594-m001527">A Design Approach to Creating Scalable Beyond-4K Video Processing Systems on FPGAs</cite>, SMPTE Meetings and Conferences ( October 2013); SMPTE, 2013
<span class="doi">10.5594/M001527</span>
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