A Parallel Processing Architecture for HDTV Encoding System

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Publisher: SMPTE — White Plains, NY
Doc Type: Conference Paper
Content Type: Original Research
Volume: 1996, No. 14A, pp. 133–140
Abstract: We propose a parallel processing architecture to encode HDTV(High Definition TV) signals by dividing input signals into several sub-pictures. Each sub-picture is encoded in parallel by a sub-picture encoding module(SEM) which has the capability to encode video signals according to MPEG-2 MP@ML(Main Profile at Main Level) specification. Each SEM consists of application specific integrated circuits(ASIC) we developed. The bit streams generated by sub-picture encoding modules are assembled into a single bit stream complying with the MPEG-2 MP@HL(Main Profile at High Level) specification. We also present a rate control scheme for parallel encoding.
Publication Date: 1996-10-01
DOI: 10.5594/M001244
Link: https://doi.org/10.5594/M001244
Author(s): Chieteuk AhnElectronics and Telecommunications Research Institute 161 Kajong-dong, Yusong-gu, Taejon, 305-350, Korea
Hyunsik ChangElectronics and Telecommunications Research Institute 161 Kajong-dong, Yusong-gu, Taejon, 305-350, Korea
Jin-Young YangElectronics and Telecommunications Research Institute 161 Kajong-dong, Yusong-gu, Taejon, 305-350, Korea
Keyword(s): HDTV, MPEG
Copyright: © 1996 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

1. Chieteuk Ahn Jae Yeal Nam Yong Han Kim , “A development of HDTV transmission standard in Korea,” Proceedings of International Workshop on HDTV '92 , Vol. I , pp. 12-1 ∼ 12-5 , Kawasaki Japan, Nov. 1992 . EXTERNAL
2. ISO/IEC JTC1/SC29/WG11 , “Test Model 5,” pp. 54 – 57 , April, 1993 . EXTERNAL

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Chieteuk Ahn, Hyunsik Chang, and Jin-Young Yang; A Parallel Processing Architecture for HDTV Encoding System, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996. Available at https://doi.org/10.5594/M001244

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Chieteuk Ahn, Hyunsik Chang, and Jin-Young Yang; A Parallel Processing Architecture for HDTV Encoding System, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996. Available at https://doi.org/10.5594/M001244

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<span class="citation">Chieteuk Ahn, Hyunsik Chang, and Jin-Young Yang; <cite>A Parallel Processing Architecture for HDTV Encoding System</cite>, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996. Available at <a href="https://doi.org/10.5594/M001244" target="_blank" rel="noopener">https://doi.org/10.5594/M001244</a></span>

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Chieteuk Ahn, Hyunsik Chang, and Jin-Young Yang; A Parallel Processing Architecture for HDTV Encoding System, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996
doi: 10.5594/M001244
url: https://doi.org/10.5594/M001244

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<li>
Chieteuk Ahn, Hyunsik Chang, and Jin-Young Yang; <cite id="bib-10-5594-m001244">A Parallel Processing Architecture for HDTV Encoding System</cite>, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996
<span class="doi">10.5594/M001244</span>
</li>