A Programmable Video DSP Architecture for HDTV Applications

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Publisher: SMPTE — White Plains, NY
Doc Type: Conference Paper
Content Type: Original Research
Volume: 1996, No. 14A, pp. 117–122
Abstract: This paper describes a programmable DSP for real-time HDTV signal processing. The SIMD architecture with 4320 processor elements operates at 50 MHz with a peak performance of 216 GBOPS (Giga Bit Operations per Second). The single chip DSP can be used for various HDTV applications such as for noise reduction, color space conversion and format conversion (HDTV to/from NTSC).
Publication Date: 1996-10-01
DOI: 10.5594/M001242
Link: https://doi.org/10.5594/M001242
Author(s): Takao YamazakiMedia Processing Laboratories, Sony Corporation. 6-7-35, Kita-shinagawa, Shinagawa, 141 Tokyo, Japan
Akihiko HashiguchiMedia Processing Laboratories, Sony Corporation. 6-7-35, Kita-shinagawa, Shinagawa, 141 Tokyo, Japan
Masuyoshi KurokawaMedia Processing Laboratories, Sony Corporation. 6-7-35, Kita-shinagawa, Shinagawa, 141 Tokyo, Japan
Ken'ichiro NakamuraMedia Processing Laboratories, Sony Corporation. 6-7-35, Kita-shinagawa, Shinagawa, 141 Tokyo, Japan
Hiroshi OkudaMedia Processing Laboratories, Sony Corporation. 6-7-35, Kita-shinagawa, Shinagawa, 141 Tokyo, Japan
Seiichiro IwaseMedia Processing Laboratories, Sony Corporation. 6-7-35, Kita-shinagawa, Shinagawa, 141 Tokyo, Japan
Copyright: © 1996 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

[1] Childers J. , “SVP: Serial Video Processor” , IEEE 1990 Custom Integrated Circuits Conference, pp. 17.3.1 – 4 . EXTERNAL
[2] Yamashita “A 3.84GIPS Integrated Memory Array Processor with 64 Processing Elements and a 2-Mb SRAM” , pp. 1336 – 1343 , Vol.29 , No.11 , IEEE Journal of Solid State Circuits , 11/ 1994 . EXTERNAL
[3] Kurokawa , “5.4GOPS Linear-Array-Architecture DSP for Video Format Conversion” , IEEE International Solid-State Circuit Conference, 1996 , FP 15.7. EXTERNAL

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Takao Yamazaki, Akihiko Hashiguchi, Masuyoshi Kurokawa, Ken'ichiro Nakamura, Hiroshi Okuda, and Seiichiro Iwase; A Programmable Video DSP Architecture for HDTV Applications, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996. Available at https://doi.org/10.5594/M001242

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Takao Yamazaki, Akihiko Hashiguchi, Masuyoshi Kurokawa, Ken&#x27;ichiro Nakamura, Hiroshi Okuda, and Seiichiro Iwase; A Programmable Video DSP Architecture for HDTV Applications, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996. Available at https://doi.org/10.5594/M001242

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<span class="citation">Takao Yamazaki, Akihiko Hashiguchi, Masuyoshi Kurokawa, Ken&#x27;ichiro Nakamura, Hiroshi Okuda, and Seiichiro Iwase; <cite>A Programmable Video DSP Architecture for HDTV Applications</cite>, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996. Available at <a href="https://doi.org/10.5594/M001242" target="_blank" rel="noopener">https://doi.org/10.5594/M001242</a></span>

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Takao Yamazaki, Akihiko Hashiguchi, Masuyoshi Kurokawa, Ken&#x27;ichiro Nakamura, Hiroshi Okuda, and Seiichiro Iwase; <cite id="bib-10-5594-m001242">A Programmable Video DSP Architecture for HDTV Applications</cite>, SMPTE Meetings and Conferences ( October 1996); SMPTE, 1996
<span class="doi">10.5594/M001242</span>
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