Architectures for High-Definition MPEG Encoders
Metadata
- Publisher
- SMPTE — White Plains, NY
- Doc Type
- Conference Paper
- Content Type
- Original Research
- Volume
- 1999, No. 7, pp. 202–202
- Abstract
- The paper discusses architectures for MPEG-2 encoders capable of operating at High Level as required for the transmission of high-definition television. The computational requirements of such an encoder cannot be met today by a single process; some degree of segmentation or parallel processing is required. Some designs of high-definition encoder achieve this segmentation at a system level by dividing the high-definition image among a number of standard-definition encoders and subsequently combining the encoded datastreams. This approach offers simplicity of design and may appear to offer certain advantages to the user. The paper discusses various aspects of the operation of encoders, including the coding of I-frames, the generation and coding of motion vectors, and bit allocation. It describes a number of problems with this type of segmentation, and shows that optimal efficiency cannot be achieved. The paper further suggests that the apparent user benefits are difficult to realize, and concludes that a purpose-designed “full-frame” high-definition encoder provides a superior solution.
- Publication Date
- 1999-07-01
- DOI
10.5594/M001192- Link
- https://doi.org/10.5594/M001192
- Author(s)
- Peter D. SymesTektronix USA
bio
Peter Symes gained his Bachelor of Science degree with honors in 1967 and began his career in television in the engineering department of the British Broadcasting Corporation. He worked in product management for Philips and Central Dynamics before joining Grass Valley in 1983. He is now Manager, Advanced Technology in the Tektronix Video and Networking Division with responsibilities including strategic planning, intellectual property, and technological liaison. In the latter role he represents Tektronix in many organizations including the Society of Motion Picture and Television Engineers (SMPTE) and the Advanced Television Systems Committee (ATSC). He is currently Chairman of the SMPTE Technology Committee on Systems. Symes holds patents and is the joint recipient of Emmy awards for the architecture of the digital picture processor. He is a Senior Member of the Institution of Electrical Engineers (IEEE), a Fellow of SMPTE, and in 1997 was appointed a Tektronix Fellow. He has written and presented numerous papers at industry conferences, and recently authored a book, Video Compression, published by McGraw Hill in April 1998. - Copyright
- © 1999 Society of Motion Picture and Television Engineers, Inc.
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Peter D. Symes; Architectures for High-Definition MPEG Encoders, SMPTE Meetings and Conferences ( July 1999); SMPTE, 1999. Available at https://doi.org/10.5594/M001192
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Peter D. Symes; Architectures for High-Definition MPEG Encoders, SMPTE Meetings and Conferences ( July 1999); SMPTE, 1999. Available at https://doi.org/10.5594/M001192
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Peter D. Symes; Architectures for High-Definition MPEG Encoders, SMPTE Meetings and Conferences ( July 1999); SMPTE, 1999. Available at https://doi.org/10.5594/M001192
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<span class="citation">Peter D. Symes; <cite>Architectures for High-Definition MPEG Encoders</cite>, SMPTE Meetings and Conferences ( July 1999); SMPTE, 1999. Available at <a href="https://doi.org/10.5594/M001192" target="_blank" rel="noopener">https://doi.org/10.5594/M001192</a></span>
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Peter D. Symes; Architectures for High-Definition MPEG Encoders, SMPTE Meetings and Conferences ( July 1999); SMPTE, 1999
doi: 10.5594/M001192
url: https://doi.org/10.5594/M001192
doi: 10.5594/M001192
url: https://doi.org/10.5594/M001192
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<li> Peter D. Symes; <cite id="bib-10-5594-m001192">Architectures for High-Definition MPEG Encoders</cite>, SMPTE Meetings and Conferences ( July 1999); SMPTE, 1999 <span class="doi">10.5594/M001192</span> </li>