SMPTE Motion Imaging Journal ( Volume: 132, Issue: 1, 2023)
[ACTIVE]
Tighter NIC/GPU Integration Yields Next-Level Media Processing Performance
Metadata
- Publisher
- SMPTE — White Plains, NY, USA
- Doc Type
- Journal Article
- Content Type
- Original Research
- Abbreviated Title
- SMPTE Mot. Imag. J
- Volume
- 132, No. 1, pp. 59–68
- Abstract
- As the media industry further consolidates building services based on commercial-off-the-shelf (COTS) hardware, the requirement for increasing performance continues to accelerate. The processing of video resolutions up to ultra-high definition (HD) (UHD) and 8K, higher frame rates, increased bit depth, and high-dynamic-range (HDR) imagery requires tighter integration and optimization between the network interface controller (NIC) and the graphical processing unit (GPU). Combined with simultaneous input and output of multiple streams; this creates the potential for performance bottlenecks that must be unlocked. This article describes how COTS hardware platforms running Graphics Processing Unit (GPU)s alongside ST 2059–2 Precision Time Protocol (PTP) locked Network Interface Cards (NIC)s, which are accurately pacing packets according to ST 2110–21 requirements, may further increase their performance throughput by reducing central processing unit (CPU)-driven data copy overhead and, in doing so, they reduce processing latency and jitter as well as more effectively use GPU resources while freeing up CPU resources.
- Publication Date
- 2023-01-01
- DOI
10.5594/JMI.2022.3196732- ISSN
- Print:
1545-0279| Electronic:2160-2492 - Link
- https://doi.org/10.5594/JMI.2022.3196732
- Author(s)
- Thomas Kernen
bio
Thomas Kernen is a senior staff architect with NVIDIA, Zurich, Switzerland. His main area of focus is defining architectures for transforming the broadcast industry into an all-IP infrastructure. He is a SMPTE Fellow, a standards director, a former chair of SMPTE’s 32NF Technology Committee, the chair of the RP 2059–15 PTP Monitoring Drafting Group, and a member of the IEEE Communications and Broadcast Societies. He served for many years as the editor of the Digital Video Broadcasting (DVB), Geneva, Switzerland, TS 101 154 “Specification for the use of Video and Audio Coding in Broadcasting Applications based on the MPEG-2 Transport Stream” supported by millions of digital receivers worldwide. Additionally, he has authored over 20 publications in leading journals and holds multiple patents that cover network, timing, and video coding optimizations for media transport and delivery. He is a frequent speaker at leading industry events both in the broadcast and networking industries. Before joining Mellanox (acquired by NVIDIA), Yokneam, Israel, he spent over 20 years in the IP industry including driving Cisco’s entry into live media production, founding internet service providers, telecom carriers, and architecting fiber to the home networks.Thomas Truebio
Thomas True is a senior applied engineer for professional video and image processing with NVIDIA’s Enterprise Solutions Group, Santa Clara, CA. In this role, he works at the intersection of video I/O and GPU, where he focuses on the integration of GPU and networking technologies into broadcast, video, and film applications ranging from previsualization to postproduction and live to air. Before joining NVIDIA, he was an applications engineer with SGI, Mountain View, CA. He has an MS degree in computer science from the Graphics Laboratory, Brown University, Providence, RI, and a BS degree from the Rochester Institute of Technology, Rochester, NY. He has spoken on the application of the GPU in broadcast and postproduction at the SMPTE Annual Technical Conference and SMPTE Section Meetings. - Keyword(s)
- ST 2110, Data Processing Unit (DPU), GPU, NIC, PTP, Timing
- Copyright
- © 2023 SMPTE
Bibliographic Reference(s)
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- IETF RFC 4566 [Superseded*]
- SMPTE ST 2059-2:2020 [Active]
- SMPTE ST 2110-10:2017 [Superseded]
- SMPTE ST 2110-20:2017 [Superseded]
- SMPTE ST 2110-21:2017 [Superseded]
- SMPTE ST 2110-22:2019 [Superseded]
- SMPTE ST 2110-30:2017 [Superseded]
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Thomas Kernen and Thomas True; Tighter NIC/GPU Integration Yields Next-Level Media Processing Performance, SMPTE Motion Imaging Journal ( Volume: 132, Issue: 1, 2023); SMPTE, 2023. Available at https://doi.org/10.5594/JMI.2022.3196732
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Thomas Kernen and Thomas True; Tighter NIC/GPU Integration Yields Next-Level Media Processing Performance, SMPTE Motion Imaging Journal ( Volume: 132, Issue: 1, 2023); SMPTE, 2023. Available at https://doi.org/10.5594/JMI.2022.3196732
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Thomas Kernen and Thomas True; Tighter NIC/GPU Integration Yields Next-Level Media Processing Performance, SMPTE Motion Imaging Journal ( Volume: 132, Issue: 1, 2023); SMPTE, 2023. Available at https://doi.org/10.5594/JMI.2022.3196732
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<span class="citation">Thomas Kernen and Thomas True; <cite>Tighter NIC/GPU Integration Yields Next-Level Media Processing Performance</cite>, SMPTE Motion Imaging Journal ( Volume: 132, Issue: 1, 2023); SMPTE, 2023. Available at <a href="https://doi.org/10.5594/JMI.2022.3196732" target="_blank" rel="noopener">https://doi.org/10.5594/JMI.2022.3196732</a></span>
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Thomas Kernen and Thomas True; Tighter NIC/GPU Integration Yields Next-Level Media Processing Performance, SMPTE Motion Imaging Journal ( Volume: 132, Issue: 1, 2023); SMPTE, 2023
doi: 10.5594/JMI.2022.3196732
url: https://doi.org/10.5594/JMI.2022.3196732
doi: 10.5594/JMI.2022.3196732
url: https://doi.org/10.5594/JMI.2022.3196732
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<li> Thomas Kernen and Thomas True; <cite id="bib-10-5594-jmi-2022-3196732">Tighter NIC/GPU Integration Yields Next-Level Media Processing Performance</cite>, SMPTE Motion Imaging Journal ( Volume: 132, Issue: 1, 2023); SMPTE, 2023 <span class="doi">10.5594/JMI.2022.3196732</span> </li>