Multiplier-Adder LSI for Digital Video Processing

Metadata

Publisher: SMPTE — White Plains, NY, USA
Doc Type: Journal Article
Content Type: Original Research
Abbreviated Title: J SMPTE
Volume: 93, No. 1A, pp. 174–186
Publication Date: 1984-01-01
DOI: 10.5594/J16817
ISSN: Print: 0036-1682
Link: https://doi.org/10.5594/J16817
Author(s): Seiichiro IwaseSony Corporation, Atsugi Plant Kanagawa-ken, Japan
bio
Seiichiro lwase was born in 1951 in Tokyo, Japan. He received the B.S. degree in electrical engineering from Chiba University in 1974 and joined Oki Industry Co., Ltd. as an engineer of digital signal processing. In 1979 he joined Sony Corp. to work on digital video tape recording. At present he is working on digital video signal processing in Information Systems Research Center, Atsugi Plant.
Ichiro KumataSony Corporation, Atsugi Plant Kanagawa-ken, Japan
bio
Ichiro Kumata was born in Osaka, Japan, in 1955. He received the B.S. and M.S. degrees in Electrical Engineering from Keio University, Yokohama, Japan, in 1978 and 1980, respectively. He joined Sony Corp., Atsugi, Japan in 1980, where he has been working on the logic design of MOS LSIs for signal processors, microprocessors and microcontrollers.
Yoshitaka HashimotoSony Corporation, Atsugi Plant Kanagawa-ken, Japan
bio
Yoshitaka Hashimoto is Assistant General Manager of the Information Systems Research Center, Sony Corp. He was born in 1940 in Kyoto, Japan. He received the B.S. degree in Electronic Engineering from the University of Electro-Communications, Tokyo in 1964, andjoined Sony Corp. Research Division in the same year. In 1968 he received the M.S. degree in Electrical Engineering from Stanford University, California after one year's study with the scholarship from Sony Corp. From 1972 to 1978 he was involved in the research work on digital signal processing of audio and video signals at the Sony Research Center. Since 1978 he has been involved in the development of digital video processing and record technology at Atsugi Plant.
Copyright: © 1984 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

1. Hashimoto Y. , “Digital Decoding and Encoding of the NTSC Signal at 912 Samples per Line” , SMPTE Journal , Oct. 81, pp 942 – 944 . EXTERNAL

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Seiichiro Iwase, Ichiro Kumata, and Yoshitaka Hashimoto; Multiplier-Adder LSI for Digital Video Processing, SMPTE Journal ( Volume: 93, Issue: 1A, January 1984); SMPTE, 1984. Available at https://doi.org/10.5594/J16817

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Seiichiro Iwase, Ichiro Kumata, and Yoshitaka Hashimoto; Multiplier-Adder LSI for Digital Video Processing, SMPTE Journal ( Volume: 93, Issue: 1A, January 1984); SMPTE, 1984. Available at https://doi.org/10.5594/J16817

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<span class="citation">Seiichiro Iwase, Ichiro Kumata, and Yoshitaka Hashimoto; <cite>Multiplier-Adder LSI for Digital Video Processing</cite>, SMPTE Journal ( Volume: 93, Issue: 1A, January 1984); SMPTE, 1984. Available at <a href="https://doi.org/10.5594/J16817" target="_blank" rel="noopener">https://doi.org/10.5594/J16817</a></span>

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Seiichiro Iwase, Ichiro Kumata, and Yoshitaka Hashimoto; <cite id="bib-10-5594-j16817">Multiplier-Adder LSI for Digital Video Processing</cite>, SMPTE Journal ( Volume: 93, Issue: 1A, January 1984); SMPTE, 1984
<span class="doi">10.5594/J16817</span>
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