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SMPTE Journal ( Volume: 103, Issue: 8, August 1994)
[ACTIVE]

D-5: 1/2-in. Full Bit Rate Component VTR Format

Metadata

Publisher
SMPTE — White Plains, NY, USA
Doc Type
Journal Article
Content Type
Original Research
Abbreviated Title
SMPTE J
Volume
103, No. 8, pp. 507–516
Abstract
The D-5 VTR, the design of which is based on the D-3 format, is a high picture quality device that uses 1/2-in. tape for full-bit recording. This article deals with the need for a full-bit recording VTR and discusses in detail the signal-processing format employed by the D-5 format. In an environment where degradation-free 10-bit digital component signals are processed, it is necessary to use a full-bit VTR that is capable of 10-bit recording. To accomplish this, D-5 processes cosited luminance and color difference samples as a unit, performs 10-bit to 8-bit data conversion without truncation, and utilizes a new technique called “video randomization. ” D-5 maintains compatibility with the composite D-3 format without technical or economic compromise, while also fully exploiting the power of the 10-bit serial digital interface.
Publication Date
1994-08-01
DOI
10.5594/J06460
ISSN
Print: 0036-1682
Link
https://doi.org/10.5594/J06460
Author(s)
K. SuesadaMatsushita Electric Industrial Co., Ltd., Osaka, Japan.
K. IshidaMatsushita Electric Industrial Co., Ltd., Osaka, Japan.
J. TakeuchiMatsushita Electric Industrial Co., Ltd., Osaka, Japan.
I. OguraMatsushita Electric Industrial Co., Ltd., Osaka, Japan.
P. LivingstonPanasonic Broadcast & Television Systems Co., Secaucus, NJ 07094
Copyright
© 1994 Society of Motion Picture and Television Engineers, Inc.
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K. Suesada, K. Ishida, J. Takeuchi, I. Ogura, and P. Livingston; D-5: 1/2-in. Full Bit Rate Component VTR Format, SMPTE Journal ( Volume: 103, Issue: 8, August 1994); SMPTE, 1994. Available at https://doi.org/10.5594/J06460
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K. Suesada, K. Ishida, J. Takeuchi, I. Ogura, and P. Livingston; D-5: 1/2-in. Full Bit Rate Component VTR Format, SMPTE Journal ( Volume: 103, Issue: 8, August 1994); SMPTE, 1994. Available at https://doi.org/10.5594/J06460

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K. Suesada, K. Ishida, J. Takeuchi, I. Ogura, and P. Livingston; D-5: 1/2-in. Full Bit Rate Component VTR Format, SMPTE Journal ( Volume: 103, Issue: 8, August 1994); SMPTE, 1994. Available at https://doi.org/10.5594/J06460
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<span class="citation">K. Suesada, K. Ishida, J. Takeuchi, I. Ogura, and P. Livingston; <cite>D-5: 1/2-in. Full Bit Rate Component VTR Format</cite>, SMPTE Journal ( Volume: 103, Issue: 8, August 1994); SMPTE, 1994. Available at <a href="https://doi.org/10.5594/J06460" target="_blank" rel="noopener">https://doi.org/10.5594/J06460</a></span>

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K. Suesada, K. Ishida, J. Takeuchi, I. Ogura, and P. Livingston; D-5: 1/2-in. Full Bit Rate Component VTR Format, SMPTE Journal ( Volume: 103, Issue: 8, August 1994); SMPTE, 1994
doi: 10.5594/J06460
url: https://doi.org/10.5594/J06460
Snippet:
<li>
K. Suesada, K. Ishida, J. Takeuchi, I. Ogura, and P. Livingston; <cite id="bib-10-5594-j06460">D-5: 1/2-in. Full Bit Rate Component VTR Format</cite>, SMPTE Journal ( Volume: 103, Issue: 8, August 1994); SMPTE, 1994
<span class="doi">10.5594/J06460</span>
</li>