A New Programming Methodology for Broadcast Video Encoding Using a Massively Parallel Processor Achitecture

Metadata

Publisher: SMPTE — White Plains, NY, USA
Doc Type: Journal Article
Content Type: Original Research
Abbreviated Title: SMPTE Mot. Imag. J
Volume: 120, No. 3, pp. 45–54
Abstract: Higher quality video encoding is only one of many requirements in an industry increasingly interested in lower power consumption, upgradable standards flexibility, and lower cost. To date, meeting all needs at the same time has been unachievable, limited by inefficiencies in underlying silicon architectures and traditional programming methodologies. Legacy processing solutions using arrays of field programmable gate arrays (FPGAs), digital signal processors (DSPs), general purpose processors (GPPs), or inflexible application specific integrated circuits (ASICs) have forced designers to make feature set tradeoffs and solutions that do not scale well with increasing pixel rates. A new approach using a dataflow programming methodology and a massively parallel processor array introduces a step in improvement in meeting tomorrow's equipment requirement with respect to computationally intensive algorithms such as H.264 Hi10P, Level 4.1 or greater. This development flow allows for (1) rapid deployment, (2) software-defined implementation that is upgradable for new features or algorithm enhancements, and (3) high-quality/low power video encoding at the point of capture. We present two key components of an H.264 encoder—Context Adaptive Binary Arithmetic Coding (CABAC) and motion estimation—and demonstrate the application of the dataflow methodology on a massively parallel processor.
Publication Date: 2011-04-01
DOI: 10.5594/j18030
ISSN: Print: 1545-0279
Link: https://doi.org/10.5594/j18030
Author(s): Michael W. Bruns
bio
Michael Bruns is a senior video DSP application engineer at Coherent Logix. He has worked in the domain of video processing and video compression since 1995 and parallel computing since 2004. His role at Coherent Logix is as technical lead for video compression codec development. Before joining Coherent Logix, Bruns was a senior software engineer at Elemental Technologies where he was responsible for high-definition video encoder development using a general purpose graphics processing unit (GPU) programming model. Previously, Bruns was among the original engineers at Ambric, a fabless semiconductor manufacturer that developed a massively parallel processor array (MPPA) chip. Bruns earned a MSEE degree from the University of California, Berkeley and a BSEE from Northwestern University. He is a member of IEEE, has published eight papers and holds one patent.
Martin A. Hunt
bio
Martin Hunt is currently an image processing program manager at Coherent Logix, where he provides both programmatic and technical leadership on all image processing projects at the company. He has more than 20 years of signal/image processing and pattern recognition experience. Before joining Coherent Logix, Hunt worked at Synopsys where he led an engineering team in applying statistical software and pattern recognition tools to analyze electrical and other semiconductor manufacturing data in order to accelerate yield ramp and improve overall product yield. He also worked at at nLine Corp. as the vice president of engineering where he was responsible for the development of an automated semiconductor inspection tool based on the disruptive technology of direct-to-digital holography. Hunt has published more 20 papers. He is a senior member of IEEE, a licensed Professional Engineer and holds three patents from his work at ORNL and nLine Corp. Hunt holds a Ph.D. in electrical engineering from the University of Tennessee, an M.S.E.E. from Vanderbilt University, and a B.S.E.E. from Tennessee Technological University.
Lin Tong
bio
Lin Tong has extensive experience in the design and analysis of video coding systems and image processing algorithms. Her responsibilities at Coherent Logix include algorithm development and implementation and systems design and verification. At Coherent Logix, she has worked on projects to implement a variety of algorithms using HyperX technology including GPS anti-jam, JPEG decoding, image stabilization, and super-resolution enhancement. Tong holds a Ph.D. in electrical engineering from the University of Texas at Arlington, an M.S.E.E. from Alfred University, and a B.S.E.E. from the University of Science and Technology of China.
Keith Bindloss
bio
Keith Bindloss is a system architect at Coherent Logix. His career has evolved from his early work on digital signal processing, especially in speech recognition and coded voice messaging (vocoding) systems. His experience in DSP algorithm development and hardware implementation led to extensive work on the improvement of DSP design and architecture. He addressed the requirements of realtime processing problems and implementations by extending his efforts to System-on-Chip (SoC) architecture and development tools. Bindloss provides valuable technical leadership and effective hands-on technical development, informed by long experience in processing, microarchitecture design, and system engineering. He is the co-inventor on 7 US patents related to processor architecture. Bindloss has more than 20 years experience in product development, technology development and technical leadership of DSP VLSI systems, architectures and HW/SW development tools.
Copyright: © 2011 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

Kuon I. Rose J. , “Measuring the Gap Between FPGAs and ASICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD ), 26 ( 2 ): 203 – 215 , Feb. 2007 . EXTERNAL
Nickols J. Buck I. Garland M. Skadron K. , “Scalable Parallel Programming with CUDA,” ACM Queue , 6 ( 2 ): 40 – 53 , Mar./Apr. 2008 . EXTERNAL
ITU-T Recommendation H.264 , “Advanced Video Coding for Generic Audiovisual Services,” International Telecommunications Union , Geneva , 2005 . EXTERNAL
Kahn G. , “The Semantics of a Simple Language for Parallel Programming,” Information Processing 74 , North Holland Publishing Company : Amsterdam , pp. 471 – 475 , 1974 . EXTERNAL
Lee E. Parks T. , “Dataflow Process Networks,” Proc. of the IEEE , pp. 773 – 799 , May 1995 . EXTERNAL
Chandra R. Menon R. Dagon L. Kohr D. Maydan D. MacDonald J. , Parallel Programming in OpenMP , p. 230 , Morgan Kaufmann : San Francisco , 2001 . EXTERNAL
Butts M. , “Synchronization Through Communication in a Massively Parallel Processor Array,” IEEE Micro , 27 ( 5 ): 32 – 40 , Sept.–Oct. 2007 . EXTERNAL
Message Passing Interface Forum , “MPI: A Message-Passing Interface Standard,” http://www.mpi-forum.org . EXTERNAL
Mascarin A. Thieret S. , “Comparison of Embedded Solutions for Signal and Image Processing: GPU vs. Intel Core i7 vs. MPC8641D,” Mercury Computer Systems : http://www.mc.com/uploadedfiles/Comparison-of-embedded-solutions.pdf , 2010 . EXTERNAL
DARPA Broad Agency Announcement , “Cognitive Radio Low-Energy Signal Analysis Sensor ICs (CLAA SIC),” Microsystems Technology Office : Arlington, VA , DARPA-BAA-10-77, 8/31/2010, p. 6 . EXTERNAL
Intel Core i7 Desktop Processor Family , http://ark.intel.com . EXTERNAL
Jing Xuan Chau Lap-Pui , “An Efficient Three Step Search Algorithm for Block Motion Estimation,” IEEE Trans. Multimedia , 6 ( 3 ): 435 – 438 , June 2004 . EXTERNAL
Po L. M. Ma W. C. , “A Novel Four-Step Search Algorithm for Fast Block Motion Estimation,” IEEE Trans. CSVT , 6 ( 3 ): 313 – 317 , June 1996 . EXTERNAL
Lin C-C Lin Y-L Chang T-S , “PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding,” IEEE Inter. Conf. on ICASSP , 2 : 385 – 388 , April 2007 . EXTERNAL

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Michael W. Bruns, Martin A. Hunt, Lin Tong, and Keith Bindloss; A New Programming Methodology for Broadcast Video Encoding Using a Massively Parallel Processor Achitecture, SMPTE Motion Imaging Journal ( Volume: 120, Issue: 3, April 2011); SMPTE, 2011. Available at https://doi.org/10.5594/j18030

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Michael W. Bruns, Martin A. Hunt, Lin Tong, and Keith Bindloss; A New Programming Methodology for Broadcast Video Encoding Using a Massively Parallel Processor Achitecture, SMPTE Motion Imaging Journal ( Volume: 120, Issue: 3, April 2011); SMPTE, 2011. Available at https://doi.org/10.5594/j18030

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<span class="citation">Michael W. Bruns, Martin A. Hunt, Lin Tong, and Keith Bindloss; <cite>A New Programming Methodology for Broadcast Video Encoding Using a Massively Parallel Processor Achitecture</cite>, SMPTE Motion Imaging Journal ( Volume: 120, Issue: 3, April 2011); SMPTE, 2011. Available at <a href="https://doi.org/10.5594/j18030" target="_blank" rel="noopener">https://doi.org/10.5594/j18030</a></span>

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Michael W. Bruns, Martin A. Hunt, Lin Tong, and Keith Bindloss; <cite id="bib-10-5594-j18030">A New Programming Methodology for Broadcast Video Encoding Using a Massively Parallel Processor Achitecture</cite>, SMPTE Motion Imaging Journal ( Volume: 120, Issue: 3, April 2011); SMPTE, 2011
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