A 2/3″ 9.5 Mpixel CMOS Imager with High Frame Rate and HDR Capabilities

Metadata

Publisher: SMPTE — White Plains, NY, USA
Doc Type: Conference Paper
Content Type: Original Research
Volume: 2020, No. 11, pp. 1–9
Abstract: Requirements for live sports production in 4K UHD resolution and high dynamic range (HDR) have multiple challenges for the imaging technology. First and foremost, the high pixel count on any given 2/3″ imager size reduces the pixel size to a critical level, while allowing for enough sensitivity and dynamic range required for many different shooting conditions. In addition, stretching the requirements even further, we have high-speed cameras fully integrated into the production workflow supporting native 4K UHD resolution as well as support for the different HDR formats used in live production. — An increase in frame rate increases the bandwidth requirements with the same factor and going from single speed to 3X or 6X speed requires clock rates exceeding the capabilities of the typical 2/3″ imagers used today. The imager presented in this paper demonstrates an architecture that supports high spatial and high temporal resolution and a high output data rate. The sensor is manufactured in a 110/180 nm CMOS process and supports a pixel rate of 3.6 Gpix/s, which translates to an output data rate of 58 Gb/s. The imager uses 4T-4shared pixels in combination with kTC-noise suppression by Digital Double Sampling (DDS) and one 16-bit ADC for each column of the shared pixels. This translates to 2112 ADC outputs which has to be multiplexed and serialized to 16 parallel outputs in 32 LVDS lanes at 1.8 Gb/s for which sixteen 132:1 multiplexers are needed. — To meet the lag performance for demanding live broadcast applications, typically a transfer time of <1 μs is needed. For high frame rate at full resolution, the available time for column settling and A/D conversion makes it impossible to meet this requirement without addressing multiple rows at the same time. To fulfill the transfer time requirements, an innovative row addressing scheme has been developed to toggle between the different rows. — This paper will explain the architecture and readout schemes used to realize a 2/3″ 9.5Mpixel CMOS imager with 3.6 Gpix/s enabling high frame-rate operation in native 4K UHD resolution and full HDR support.
Publication Date: 2020-11-10
DOI: 10.5594/M001905
Link: https://doi.org/10.5594/M001905
Author(s): Klaus WeberPrincipal, Camera Solutions & Technology, Grass Valley, Germany
Jeroen RotteGroup Leader, Image Sensors, Grass Valley, Netherlands
Keyword(s): 4K, HDR, CMOS Imagers, Imagers, Pixel, Super-slow-motion (SSM)
Copyright: © 2020 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

4K, HDR and Further Image Enhancements for Live Image Acquisition [Active]
J. Rotte et al. “Differential Digital Double sampling readout scheme for a 4T 4-shared pixel with reduced interconnection.” P05, IISW, May 2015. EXTERNAL
K. Weber, Dr. Ir. P. Centen, “A 4K UHD 2/3-inch CMOS imager with Dynamic Pixel Management - an Enabler for New Format Flexibility”, SMPTE 2016 Annual Technical Conference & Exhibition, October 2016 EXTERNAL
S. Louwsma et al. “A scalable 12b-16b charge-domain multi-slope column ADC for HDR imagers with 86dB DR at 1 μs conversion time”, IISW, 2019. EXTERNAL

Source Data (JSON)

Full registry record with provenance metadata. Open directly: /api/doc/10.5594-M001905.json

Reference Tree

Explore all references and references to this document, as a navigable tree.

Open Reference Tree

Reference this Doc

Plain text (ISO 690 compliant)

Preview:

Klaus Weber and Jeroen Rotte; A 2/3″ 9.5 Mpixel CMOS Imager with High Frame Rate and HDR Capabilities, SMPTE Meetings and Conferences ( November 2020); SMPTE, 2020. Available at https://doi.org/10.5594/M001905

Snippet:

Klaus Weber and Jeroen Rotte; A 2/3″ 9.5 Mpixel CMOS Imager with High Frame Rate and HDR Capabilities, SMPTE Meetings and Conferences ( November 2020); SMPTE, 2020. Available at https://doi.org/10.5594/M001905

HTML (ISO 690 compliant)

Preview:

Snippet:

<span class="citation">Klaus Weber and Jeroen Rotte; <cite>A 2/3″ 9.5 Mpixel CMOS Imager with High Frame Rate and HDR Capabilities</cite>, SMPTE Meetings and Conferences ( November 2020); SMPTE, 2020. Available at <a href="https://doi.org/10.5594/M001905" target="_blank" rel="noopener">https://doi.org/10.5594/M001905</a></span>

SMPTE's HTML Pub

Preview:

Klaus Weber and Jeroen Rotte; A 2/3″ 9.5 Mpixel CMOS Imager with High Frame Rate and HDR Capabilities, SMPTE Meetings and Conferences ( November 2020); SMPTE, 2020
doi: 10.5594/M001905
url: https://doi.org/10.5594/M001905

Snippet:

<li>
Klaus Weber and Jeroen Rotte; <cite id="bib-10-5594-m001905">A 2/3″ 9.5 Mpixel CMOS Imager with High Frame Rate and HDR Capabilities</cite>, SMPTE Meetings and Conferences ( November 2020); SMPTE, 2020
<span class="doi">10.5594/M001905</span>
</li>