GPU Accelerated H.264 Video Compression for Broadcast

Metadata

Publisher: SMPTE — White Plains, NY
Doc Type: Conference Paper
Content Type: Original Research
Volume: 2010, No. 10, pp. 1–16
Abstract: In recent years the ability to perform massive parallel computations has become readily available on every desktop due to improved graphic processors and new programming tools like CUDA. The standard CPUs are also evolving rapidly in the same direction, making this technology even more accessible. Video compression is an illustrative example of an area where the speed / computation power trade off is especially steep. To render all the features of the modern H.264 compression standard a super-computing level of power might be necessary. The modern GPU and the next generation of the CPU could deliver the required computation power. We investigate what can be done to exploit the features of the modern GPUs for H.264 compression and how the new video compression standards like H.265 might be adopted in the future of massive parallel processing
Publication Date: 2010-10-01
DOI: 10.5594/M001388
Link: https://doi.org/10.5594/M001388
Author(s): Dmitri KlimovCinegy GmbH, Muellerstr.27, 80469 Munich, Germany
Jan WeignerCinegy GmbH, Muellerstr.27, 80469 Munich, Germany
Keyword(s): H.264, H.265, MPEG-2, GPU
Copyright: © 2010 Society of Motion Picture and Television Engineers, Inc.

Bibliographic Reference(s)

1. Intel Advanced Vector Extensions Programming Reference. EXTERNAL
10. H265.net http://www.h265.net . EXTERNAL
11. Nvidia Speed Results: http://www.mainconcept.com/fileadmin/user_upload/download/product_sheets/CUDA-Sheets_06-2010.pdf , 2010. EXTERNAL
12. Cinegy Cinecoder: www.cinecoder.com . EXTERNAL
13. ELEMENTAL, Harness the power of massively parallel video processing: http://www.elementaltechnologies.com/products/product-overview . EXTERNAL
14. Bailey David H. , A High-Performance FFT Algorithm for Vector Supercomputers-Abstract, Proceedings of the Third SIAM Conference on Parallel Processing for Scientific Computing, p. 114 , December 01–04, 1987 . EXTERNAL
15. Franchetti F. Püschel M. Voronenko Y. Chellappa S. Moura J. M. F. Discrete Fourier transform on multicore . IEEE Signal Processing Magazine, special issue on “Signal Processing on Platforms with Multiple Cores” , 26 ( 6 ): 90 – 102 , 2009 . EXTERNAL
16. Frigo M. Steven Johnson G. The design and implementation of fftw3 . In Proceedings of the IEEE , volume 93 , pages 216 – 231 , 2005 . EXTERNAL
17. Genovese L. Graphic processing units: A possible answer to HPC . In 4th ABINIT Developer Workshop, 2009 . EXTERNAL
18. Govindaraju Naga K. Lloyd Brandon Dotsenko Yuri Smith Burton Manferdelli John , High performance discrete Fourier transforms on graphics processors , Proceedings of the 2008 ACM/IEEE conference on Supercomputing, November 15–21, 2008 , Austin, Texas. EXTERNAL
19. Johnson J. R. Johnson R. W. Rodriquez D. Tolimieri R. , A methodology for designing, modifying, and implementing Fourier transform algorithms on various architectures , Circuits, Systems, and Signal Processing , v. 9 n. 4 , p. 449 – 500 , 1990 [doi>10.1007/BF01189337]. EXTERNAL
2. Intel. SSE4 Programming Reference. 2007 . EXTERNAL
20. Kumar Sanjeev Kim Daehyun Smelyanskiy Mikhail Chen Yen-Kuang Chhugani Jatin Hughes Christopher J. Kim Changkyu Lee Victor W. Nguyen Anthony D. , Atomic Vector Operations on Chip Multiprocessors , Proceedings of the 35th Annual International Symposium on Computer Architecture, p. 441 – 452 , June 21–25, 2008 [doi>10.1109/ISCA.2008.38]. EXTERNAL
21. Ramanathan R. Extending the world's most popular processor architecture . Intel Whitepaper. EXTERNAL
22. Satish Nadathur Kim Changkyu Chhugani Jatin Nguyen Anthony D. Lee Victor W. Kim Daehyun Dubey Pradeep , Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort, Proceedings of the 2010 international conference on Management of data, June 06–10, 2010 , Indianapolis, Indiana, USA [doi>10.1145/1807167.1807207]. EXTERNAL
23. Seiler Larry Carmean Doug Sprangle Eric Forsyth Tom Abrash Michael Dubey Pradeep Junkins Stephen Lake Adam Sugerman Jeremy Cavin Robert Espasa Roger Grochowski Ed Juan Toni Hanrahan Pat , Larrabee: a many-core x86 architecture for visual computing , ACM Transactions on Graphics (TOG) , v. 27 n. 3 , August 2008 [doi>10.1145/1360612.1360617]. EXTERNAL
24. Silberstein Mark Schuster Assaf Geiger Dan Patney Anjul Owens John D. , Efficient computation of sum-products on GPUs through software-managed cache , Proceedings of the 22nd annual international conference on Supercomputing, June 07–12, 2008 , Island of Kos, Greece [doi>10.1145/1375527.1375572]. EXTERNAL
25. Volkov V. Demmel J. LU, QR and Cholesky Factorizations using Vector Capabilities of GPUs . Technical Report UCB/EECS-2008-49, EECS Department, University of California , Berkeley , May 2008 . EXTERNAL
26. Volkov Vasily Demmel James W. , Benchmarking GPUs to tune dense linear algebra , Proceedings of the 2008 ACM/IEEE conference on Supercomputing, November 15–21, 2008 , Austin, Texas. EXTERNAL
27. Williams Samuel Waterman Andrew Patterson David , Roofline: an insightful visual performance model for multicore architectures , Communications of the ACM , v. 52 n. 4 , April 2009 [doi>10.1145/1498765.1498785]. EXTERNAL
28. Xu W. Mueller K. A performance-driven study of regularization methods for gpu-accelerated iterative ct . In Workshop on High Performance Image Reconstruction (HPIR), 2009 . EXTERNAL
29. Yang Zhiyi Zhu Yating Pu Yong , Parallel Image Processing Based on CUDA , Proceedings of the 2008 International Conference on Computer Science and Software Engineering, p.198–201, December 12–14, 2008 [doi>10.1109/CSSE.2008.1448]. EXTERNAL
3. Leischner N. Osipov V. Sanders P. Fermi Architecture White Paper, 2009 . EXTERNAL
4. NVIDIA CUDA Zone . http://www.nvidia.com/object/cuda_home.html , 2010 . EXTERNAL
5. General-purpose computation on graphics hardware . http://gpgpu.org , 2009 . EXTERNAL
6. CUDA BLAS Library: http://developer.download.nvidia.com/compute/cuda/2_1/toolkit/docs/CUBLAS_Library_2.1.pdf 2008. EXTERNAL
7. CUDA CUFFT Library: http://developer.download.nvidia.com/compute/cuda/2_1/toolkit/docs/CUFFT_Library_2.1.pdf 2008. EXTERNAL
8. ISO/IEC 14496–10. EXTERNAL
9. Draft meeting report for 31st VCEG Meeting (Marrakech, MA, 15–16 January 2007 ). EXTERNAL

Source Data (JSON)

Full registry record with provenance metadata. Open directly: /api/doc/10.5594-M001388.json

Reference Tree

Explore all references and references to this document, as a navigable tree.

Open Reference Tree

Reference this Doc

Plain text (ISO 690 compliant)

Preview:

Dmitri Klimov and Jan Weigner; GPU Accelerated H.264 Video Compression for Broadcast, SMPTE Meetings and Conferences ( October 2010); SMPTE, 2010. Available at https://doi.org/10.5594/M001388

Snippet:

Dmitri Klimov and Jan Weigner; GPU Accelerated H.264 Video Compression for Broadcast, SMPTE Meetings and Conferences ( October 2010); SMPTE, 2010. Available at https://doi.org/10.5594/M001388

HTML (ISO 690 compliant)

Preview:

Dmitri Klimov and Jan Weigner; GPU Accelerated H.264 Video Compression for Broadcast, SMPTE Meetings and Conferences ( October 2010); SMPTE, 2010. Available at https://doi.org/10.5594/M001388

Snippet:

<span class="citation">Dmitri Klimov and Jan Weigner; <cite>GPU Accelerated H.264 Video Compression for Broadcast</cite>, SMPTE Meetings and Conferences ( October 2010); SMPTE, 2010. Available at <a href="https://doi.org/10.5594/M001388" target="_blank" rel="noopener">https://doi.org/10.5594/M001388</a></span>

SMPTE's HTML Pub

Preview:

Dmitri Klimov and Jan Weigner; GPU Accelerated H.264 Video Compression for Broadcast, SMPTE Meetings and Conferences ( October 2010); SMPTE, 2010
doi: 10.5594/M001388
url: https://doi.org/10.5594/M001388

Snippet:

<li>
Dmitri Klimov and Jan Weigner; <cite id="bib-10-5594-m001388">GPU Accelerated H.264 Video Compression for Broadcast</cite>, SMPTE Meetings and Conferences ( October 2010); SMPTE, 2010
<span class="doi">10.5594/M001388</span>
</li>